Debug via CPM PCIe Interface - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

In data center applications and other PCIe interface-hosted systems, the DPC can be accessed via the same PCIe interface in the CPM that is used for host-to-adaptive SoC communication. You can choose how to map the debug function to a PCIe physical function and BAR space. The debug function includes a dedicated PCIe HSDP DMA engine that is used to move debug data between the DPC and host memory.

Note: CPM availability is device specific. For information, see the Versal Architecture and Product Data Sheet: Overview (DS950).