Overview - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

Performance modeling is a method to analyze system-level performance and latency by mimicking the application traffic flow using traffic generators, checkers, and performance monitor blocks.

In Versal adaptive SoC, the high-speed NoC interface provides fixed connectivity to embedded hard blocks and programmable connectivity to PL blocks, DSPs, MRMAC (via PL routes), and AI Engines (via PL streams). Each NoC interface is capable of interfacing with an AXI4-based master or slave device that supports memory mapped or streaming transactions.

For system-level performance analysis, it is important to model the traffic flow going through the NoC, from the dynamic random access memory (DRAM) to the Versal adaptive SoC processing hardware blocks.

All of the following resource blocks in the Versal adaptive SoC can access data from the DRAM using the NoC:

  • Processing system (PS)
  • Accelerator hardware blocks (like DSPs and AI Engines)
  • PCIe interface-based endpoint direct memory access (DMAs)
  • High-speed MRMAC blocks