Packaging the RTL Design - 2024.1 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2024-05-30
Version
2024.1 English

The final step in the HLS component flow is to package the RTL design into a form that can be used by other tools in the design flow, such as in the Vivado Design Suite as part of a larger system design. Click the Package command in the Flow Navigator to export the RTL as a Vivado IP, Vitis kernel, or a synthesized checkpoint.

Configure Packaging

You can configure the packaging process to export the IP or kernel according to your settings prior to running package. The Config File Editor separates Packaging into Output and IP sections as shown below.

Figure 1. Config File Package Settings

Specifying the Output Format and Output File

The output.format for the RTL synthesis results must be specified. The default format is RTL, which lets the tool synthesize the Verilog and VHDL code from the C/C++ source files, but does not generate the Vivado IP or Vitis kernel as an output product. This approach lets you run synthesis quickly without having to generate hardware files at every iteration. However, to use the RTL design in downstream processes like embedded software design, or Application projects, you must generate the hardware files. The flow you are supporting in your design determines the best choice for output format.

The Package options, and their default values are listed below:

package.output.file

The output.file name and location are determined by the tool, and default to the name of the top function specified for the HLS component. However, you can specify the name and location to override the default values.

package.output.format

The output.format command supports several different formats as shown in the following table.

Table 1. Package Output Formats
Package Format Default Location Comments
package.out.format=ip_catalog <comp-name>.zip

The IP is exported as a ZIP file that can be added to the Vivado IP catalog.

The impl/ip folder also contains the contents of the unzipped IP.

package.out.format=xo <comp-name>.xo

The XO file output can be used for linking by the Vitis compiler in the application acceleration development flow.

You can link the Vitis kernel with other kernels, and the target accelerator card, to build the xclbin file for your accelerated application.

package.out.format=sysgen <comp-name>.zip

The IP is exported as a ZIP file that for use with the Vivado edition of System Generator for DSP.

The impl/ip folder also contains the contents of the unzipped IP.

package.out.format=rtl Creates Verilog and VHDL folders in the HLS component working directory. This options lets you skip the generation of the packaged IP or XO modules to save time while iterating on the initial design.
package.out.syn
Enable or disable the creation of the IP or XO during synthesis. Specify false to disable generation of the packaged IP or XO, or specify true to enable it. This options lets you skip the generation of the packaged IP or XO modules to save time while iterating on the initial design.
These selections result in the following config file entries:
[HLS]
package.output.format=xo
package.output.file=../../<filename>
package.output.syn=false

IP Configuration

When you specify package.output.format=ip_catalog in the HLS configuration file, you can also specify additional fields that will be applied to the generated IP, such as the Vendor, Library, Name, and Version (VLNV) of the IP.

The Configuration information is used to differentiate between multiple instances of the same IP when it is loaded into the Vivado IP catalog. For example, if an implementation is packaged for the IP catalog, and then a new solution is created and packaged as IP, the new solution by default has the same name and configuration information. If the new solution is also added to the IP catalog, the IP catalog will identify it as an updated version of the same IP and the last version added to the IP catalog will be used.

The IP options, and their default values are listed below:

package.ip.vendor
xilinx.com
package.ip.library
hls
package.ip.name
Default to HLS component name
package.ip.version
1.0
package.ip.description
An IP generated by HLS component
package.ip.display_name
This field left blank
package.ip.taxonomy
This field left blank
package.ip.xdc_file
This field left blank
package.ip.xdc_ooc_file
This field left blank
Tip: The packaging process in the Vitis unified IDE uses the vitis-run --mode hls --package command as described in vitis, v++, and vitis-run Commands.

After the packaging process is complete, the ZIP file archive or XO kernel is written to the specified package.output.file location, or written in the HLS component folder. The exported IP file can be imported into the Vivado IP catalog and used in any design. The exported Vitis kernel can be used with the v++ --link command as paret of a larger system design.

Software Driver Files

For designs that include AXI4-Lite slave interfaces, a set of software driver files is created during the export process. These C driver files can be included in a Vitis embedded software development project, and used to access the AXI4-Lite slave port.

The software driver files are written to directory solution/impl/ip/drivers and are included in the packaged IP export.zip. Refer to AXI4-Lite Interface for details on the C driver files.