The HLS compilation mode provides access to numerous features for the
development, optimization, analysis, and export of Vitis kernels (
.xo) or Vivado IP (.zip)
files. The HLS mode can be reached by using the following command, or by launching the
Vitis unified IDE:
v++ -c --mode hls -h [options] <input_files...>The HLS compilation options should be entered into a configuration file for
use with the v++ command using the --config option. The HLS options should be placed under a
section head of [hls] in the config file. For example
the following config file specifies the part, the source file, the test bench files, and
the flow target. Notice that part is not specified
under the [HLS] header because this is a general
option for the v++ compiler.
part=xcvu11p-flga2577-1-e
[hls]
clock=8
flow_target=vitis
syn.file=../../src/dct.cpp
syn.top=dct
tb.file=../../src/out.golden.dat
tb.file=../../src/in.dat
tb.file=../../src/dct_test.cpp
tb.file=../../src/dct_coeff_table.txt
syn.output.format=xo
clock_uncertainty=15%
Options Allowed in a Config File or on the Command Line
When working with the Vitis unified IDE the
following v++ command-line options are available
for use from within a configuration file. These options do not belong under any
header in the configuration file.
- --platform <arg>
- Specify path to a platform specification (.xpfm) to target the current component or project to.
- --freqhz <arg>
- Specify a clock frequency in Hz. Important: If your HLS configuration file specifies
platform=instead ofpart=you must use also usefreqhz=instead ofclock=. This is because the platform specifies a clock infreqhzform, and you can only override it using the same form. - --part <arg>
- Specify a target device for the HLS component.