syn.directive.loop_merge - 2024.1 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
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2024.1 English


Merges all loops into a single loop. Merging loops:

  • Reduces the number of clock cycles required in the RTL to transition between the loop-body implementations.
  • Allows the loops be implemented in parallel (if possible).

The rules for loop merging are:

  • If the loop bounds are variables, they must have the same value (number of iterations).
  • If loops bounds are constants, the maximum constant value is used as the bound of the merged loop.
  • Loops with both variable bound and constant bound cannot be merged.
  • The code between loops to be merged cannot have side effects. Multiple execution of this code should generate the same results.
    • a=b is allowed
    • a=a+1 is not allowed.
  • Loops cannot be merged when they contain FIFO reads. Merging changes the order of the reads. Reads from a FIFO or FIFO interface must always be in sequence.


syn.directive.loop_merge=[options] <location>
  • <location> is the location (in the format function[/label]) at which the loops reside.


Forces loops to be merged even when Vitis HLS issues a warning. You must assure that the merged loop will function correctly.


Merges all consecutive loops in function foo into a single loop.


All loops inside loop_2 of function foo (but not loop_2 itself) are merged by using the force option.

syn.directive.loop_merge=force foo/loop_2