HLS IP Libraries - 2024.1 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2024-05-30
Version
2024.1 English

AMD Vitis™ HLS provides C++ libraries to implement a number of AMD IP blocks. The C libraries allow the following AMD IP blocks to be directly inferred from the C++ source code ensuring a high-quality implementation in the FPGA.

Table 1. HLS IP Libraries
Library Header File Description
hls_fft.h Allows the AMD LogiCORE IP FFT to be simulated in C and implemented using the AMD LogiCORE block.
hls_fir.h Allows the AMD LogiCORE IP FIR to be simulated in C and implemented using the AMD LogiCORE block.
hls_dds.h Allows the AMD LogiCORE IP DDS to be simulated in C and implemented using the AMD LogiCORE block.
ap_shift_reg.h Provides a C++ class to implement a shift register which is implemented directly using an AMD SRL primitive.