Make sure the HLS component is active in the Flow Navigator, or select it from the Component menu to make it the active component in the tool. When the HLS component is the active component, the Flow Navigator enables running C Simulation, C Synthesis, C/RTL Co-simulation, Packaging, and Implementation to build and analyze the HLS component. Select Run beneath the IMPLEMENTATION heading in the Flow Navigator.
When the HLS compiler reports the results of high-level synthesis, it provides an estimate of the results with projected clock frequencies and resource utilization (LUTs, DSPs, BRAMs, etc). These results are only estimates because the tool cannot know what optimizations or routing delays will be in the final synthesized or implemented design. To get a better analysis of the RTL design you can actually run Vivado synthesis and place and route on the generated RTL design, and review the results of timing and resource utilization. However, even these results are only improved estimates, because the IP or kernel being used in a larger design with other IP and kernels will yield different results.
Configure Implementation
You can configure Vivado synthesis and implementation prior to running it by using the Implementation section of the Config File Editor, as shown below, or by editing the HLS config file directly.
The configuration commands for Implementation include:
- vivado.flow
- Specify to run only synthesis or both synthesis and implementation.
Synthesis alone will run faster than both synthesis and implementation, but
will lack some of details of the implementation run. The default is
syn
. - vivado.rtl
- Specifies the language to use when running Vivado out-of-context flow. The default is Verilog.
- vivado.clock
- Specify the clock period to use during synthesis or implementation. When not specified, the default clock specified when the HLS component is created is used.
- vivado.impl_strategy
- Specify the strategy to employ in the implementation run. This is only for use during the implementation run for resource utilization and timing estimates, and does not affect the generated Vivado IP or Vitis kernels.
- vivado.max_timing_paths
- Specify the number of timing paths to extract from the Timing Summary report. The specified number of worst case paths are returned.
- vivado.optimization_level
- This is a general feature to manage the optimizations performed by the Vivado tool. The higher the setting, the more optimizations are employed, and the longer the runtime as a result.
- vivado.pblock
- Specifies a Pblock range or value to use during placement and routing to limit the area available for the design.
- vivado.phys_opt
- Specify the physical optimization to run. Choices include:
none
,place
,route
, andall
- vivado.report_level
- Defines the report-level generated during synthesis or implementation. The report can include the utilization and timing summary, timing path details, or a failfast report, which is the default.
- vivado.synth_design_args
- Specify options for the
synth_design
command. - vivado.synth_strategy
- Specify the strategy to employ in the Vivado synthesis run.
Run Implementation
With the Implementation setup defined in the config file you are
ready to select Run from the
Flow Navigator. You
can track the progress of the implementation run in the Output window. The transcript for the run
will have the top function name as <component-name>::implementation
as shown below.
vitis-run --mode hls --impl
command as described in
vitis, v++, and vitis-run Commands. After the implementation is complete you should see the Implementation finished successfully message at the end of the transcript. You will also see the Reports folder under the IMPLEMENTATION heading populated with the following reports:
- Summary: Reports the command line used and the time stamp on the results
- RTL Synthesis: Reports the results of synthesis including resource use and timing
- Place and Route: As described in Implementation Report