Interface Configuration - Interface Configuration - 2026.1 English - UG1399

The syn.interface commands configure the default interface settings applied to the HLS component. These settings can be overridden for specific top-level interface ports using syn.directive.interface.

syn.interface.clock_enable

Add a clock-enable port (ap_ce) to the design. The clock enable prevents all clock operations when it is active-Low, and disables all sequential operations. The default is false.

syn.interface.clock_enable=1

syn.interface.default_axi

When set to true, the compiler infers AXI interfaces (m_axi, s_axilite, or axis) for top-level arguments that do not have an interface pragma. This option replaces flow_target for selecting interface defaults across both Vitis kernel and Vivado IP flows. The default is false.

syn.interface.default_axi=1

syn.interface.m_axi_addr64

Enables 64-bit addressing for all m_axi interfaces. The tool enables this option by default. When disabled, the m_axi interfaces uses 32-bit addressing.

syn.interface.m_axi_addr64=1

syn.interface.m_axi_alignment_byte_size

Specifies default alignment byte size for all m_axi interfaces. This setting defaults to 64 bytes for Vitis kernel flow. The default is 1 byte for the Vivado IP flow. See the Vivado/Vitis Flows section of the Vitis High-Level Synthesis User Guide (UG1399).

syn.interface.m_axi_alignment_byte_size=16

Tip: A value of 0 is not valid.

syn.interface.m_axi_auto_id_channel

Enables automatic assignment of channel IDs for m_axi interfaces. The tool enables this option by default. Refer to the AXI4 Master Interface section of the Vitis High-Level Synthesis User Guide (UG1399) for additional information.

syn.interface.m_axi_auto_id_channel=1

syn.interface.m_axi_auto_max_ports

Enables automatic creation of separate m_axi interface adapters for each argument or port on the interface.

By default, this option is off, reducing the m_axi interfaces to the minimum required set.

Refer to the section M_AXI Bundles of the Vitis High-Level Synthesis User Guide (UG1399) or more information.

syn.interface.m_axi_auto_max_ports=1

syn.interface.m_axi_buffer_impl

Specifies the implementation resource for all buffers internal to the m_axi adapters. The choices are auto, lutram, bram, uram. The default is bram.

syn.interface.m_axi_buffer_impl=lutram

syn.interface.m_axi_cache_impl

Specifies the implementation resource for cache added to the m_axi adapters. The choices are auto, lutram, bram, uram. The default is auto.

syn.interface.m_axi_cache_impl=lutram

syn.interface.m_axi_conservative_mode

Configure all m_axi adapters to work in conservative mode. The Vitis tool waits to issue a write request until the associated write data is entirely available. Typically, the tool waits until the adapter buffers the data or emits it.

The tool uses a buffer inside the M_AXI adapter to store all the data for a burst (both in case of reading and writing).

The tool enables this setting by default. Enabling this setting can resolve deadlock due to concurrent requests (read or write) on the memory subsystem. However, it can also slightly increase write latency. Disable conservative mode by setting it to false.

syn.interface.m_axi_conservative_mode=0

syn.interface.m_axi_flush_mode

Configure all m_axi adapters to be flushable, writing or reading garbage data. This option applies only when pipeline blocking interrupts a burst. For example, when missing data inputs when not in conservative mode or missing output space. The system disables this option by default.

syn.interface.m_axi_flush_mode=1

syn.interface.m_axi_latency

Specifies the expected latency of the m_axi interface globally. Allows the design to initiate a bus request a number of cycles (latency) before the read or write is expected. The default value is 64 for the Vitis Kernel flow. The default value is for the Vivado IP flow. See the section Defaults of Vivado and Vitis Flows in the Vitis High-Level Synthesis User Guide (UG1399).

syn.interface.m_axi_latency=5

syn.interface.m_axi_max_bitwidth

Specifies the maximum bitwidth for the m_axi interfaces data channel. The default is 1024 bits. The specified value must be a power-of-two, between 8 and 1024.

If the actual accesses are bigger than the required interface, throughput splits into a multi-cycle burst and throughput decreases.

syn.interface.m_axi_max_bitwidth=128

syn.interface.m_axi_max_read_burst_length

Specifies a global maximum number of data values read during a burst transfer for all m_axi interfaces. The default is 16.

syn.interface.m_axi_max_read_burst_length=12

syn.interface.m_axi_max_widen_bitwidth

Enables automatic port width resizing to widen bursts for the m_axi interface, up to the chosen bitwidth. The specified value must be a power of 2 between 8 and 1024, and must align with the -m_axi_alignment_size. The default value is 512 for the Vitis Kernel flow, and 0 for the Vivado IP flow.

syn.interface.m_axi_max_widen_bitwidth=64

syn.interface.m_axi_max_write_burst_length

Specifies a global maximum number of data values written during a burst transfer for all m_axi interfaces. The default is 16.

syn.interface.m_axi_max_write_burst_length=12

syn.interface.m_axi_min_bitwidth

Specifies the minimum bitwidth for m_axi interfaces data channel. The default is 8 bits. The value must be a power of 2, between 8 and 1024. This does not necessarily increase throughput if the actual accesses are smaller than the required interface.

syn.interface.m_axi_min_bitwidth=64

syn.interface.m_axi_num_read_outstanding

This option specifies how many read requests the design can issue to the m_axi interface without responses before stalling. This implies internal storage in the design, and a FIFO of size:

num_read_outstanding*max_read_burst_length*word_size

The default value is 16.

syn.interface.m_axi_num_read_outstanding=8

syn.interface.m_axi_num_write_outstanding

Specifies how many write requests can be made to the m_axi interface without a response, before the design stalls. This implies internal storage in the design, and a FIFO of size:

num_write_outstanding*max_write_burst_length*word_size

The default value is 16.

syn.interface.m_axi_num_write_outstanding=8

syn.interface.m_axi_offset

Specifies the default offset mechanism for all m_axi interfaces. The options are:

• off: No offset port is generated.
• slave: Generates an offset port and automatically maps it to an s_axilite interface. This option is the default value.
• direct: Generates a scalar input offset port for directly passing the address offset into the IP through the offset port.

syn.interface.m_axi_offset=slave

syn.interface.register_io

Globally enables registers for all scalar inputs, outputs, or all scalar ports on the top function. Arrays are always registered. The options are off, scalar_in, scalar_out, scalar_all. The default is off.

syn.interface.register_io=scalar_out

syn.interface.s_axilite_data64

Enables 64 bit data width for s_axilite interface. Use 1 to enable 64 bit data width and 0 to disable it. The default is 32 bit data width.

syn.interface.s_axilite_data64=1

syn.interface.s_axilite_interrupt_mode

Specifies the interrupt mode for s_axilite interface to be Clear on Read (cor) or Toggle on Write (tow). The Vitis tool can complete clear on Read interrupts in a single transaction, while tow requires two. Tow is the default interrupt mode.

syn.interface.s_axilite_interrupt_mode=cor

syn.interface.s_axilite_mailbox

Enables the creation of a mailbox for non-stream non-stable s_axilite arguments. The mailbox feature sets and manages the auto-restart kernels. See the Auto-Restarting Mode section in the Vitis High-Level Synthesis User Guide (UG1399). The available options for this setting are below.

• in: Enables mailbox for only input arguments
• out: Enables mailbox for only output arguments
• both: Enables mailbox for input and output arguments
• none: No mailbox created. This option is the default value.

syn.interface.s_axilite_mailbox=in

syn.interface.s_axilite_status_regs

Enables exposure of ECC error bits in the s_axilite register file. Achieves exposure through two clear-on-read (COR) counters per block RAM or UltraRAM with ECC enabled. The options are ecc to enable or off to disable the feature. The default is setting is disabled.

syn.interface.s_axilite_status_regs=ecc

syn.interface.s_axilite_sw_reset

Enables SW reset in s_axilite adapter.

syn.interface.s_axilite_sw_reset=1