Output of C/RTL Co-Simulation - 2024.1 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2024-05-30
Version
2024.1 English

In the Vitis unified IDE the hierarchy of the HLS component is structured as follows: <workspace>/<component>/<component>/hls/. You can select the HLS component in the Vitis Component Explorer and select Open In Terminal from the right-click menu to explore the contents of the component folders.

When C/RTL Cosimulation completes, the sim folder is created inside the solution folder. This folder contains the following elements:
  • A verification folder named sim/verilog or vhdl is created for each RTL language that is verified.
    • The RTL files used for simulation are stored in the verilog or vhdl folder.
    • The RTL simulation is executed in the verification folder.
    • Any outputs, such as trace files and waveform files, are written to the verilog or vhdl folder.
  • The sim/report folder contains the report and log file for each type of RTL simulated.
  • Additional folders sim/autowrap, tv, wrap and wrap_pc are work folders used by the HLS compiler. There are no user files in these folders.
Tip: If the cosim.setup option was selected in the config file, an executable is created in the sim/<hdl> folder but the simulation is not run. The simulation can be manually run by executing the simulation .sh or .exe in a Terminal.