In the Vitis Unified IDE , the hierarchy of the HLS component is: <workspace>/<component>/<component>/hls/ . You can select the HLS component in the Vitis Component Explorer . Select Open In Terminal from the right-click menu to explore the contents of the component folders.
Synthesis completion results in the syn folder <component>/hls folder. This folder contains the following elements.
-
The
verilog
and
vhdl
folders contain the output RTL files.
- The top-level file has the same name as the top-level function for synthesis.
- Create one RTL file each sub-function that Vitis does not inline into higher level function.
- There can be additional RTL files to implement sub-blocks of the RTL hierarchy, such as block RAM, and pipelined multipliers.
- The report folder contains a report file for the top-level function and one for every sub-function that has not been in-lined into a higher level function by the HLS compiler. The report for the top-level function provides details on the entire design.
Important:
Do not directly use the RTL
files generated in the
syn/verilog
or
syn/vhdl
folder for synthesis in the
Vivado
tool. Instead you must use the exported output files generated by the
package process as described in
Packaging the RTL Design
. The HLS
compiler sometimes uses IP from the
Vivado
IP catalog in
the synthesized RTL code, such as with floating point designs, and the
verilog
and
vhdl
folders
will not contain the complete design.