Running C Synthesis - 2024.2 English - UG1399

Specifying the Flow Target and General Settings

The HLS component can be used to create synthesis results for the Vivado IP flow, or the Vitis kernel flow. The flow target determines the default interface ports applied to the IP or kernel and other details of the synthesized design.

Figure 1. HLS Component General Settings

In the preceding figure the flow_target is currently set for the Vitis Kernel flow. The default flow target is the Vivado IP flow. This target is generally set when the HLS component is created, but can be modified as needed.

The part or platform can also be specified under the General settings. These options determine the physical device that the C/C++ code will be synthesized for. The selected device can feature hardware resources that expand or restrict the implementation choices of the RTL synthesis.

Finally, the clock period and clock_uncertainty can be specified to define the timing details of the RTL design. These can affect the timing and scheduling of operations in the design.

part=xcvc1902-vsva2197-2MP-e-S

[hls]
flow_target=vitis
clock=8ns
clock_uncertainty=15%

Loading Source Files and Identifying the Top Function

Generally the source code for the HLS component is defined or loaded at the time of creation. However, you can bypass that step when creating the component, and then you will need to add the source files prior to synthesizing the design. To add source files to an existing HLS component open the component config file and navigate to the C Synthesis sources section as shown below. This section of the Config Editor lets you add one or more source files, and specify the top function.

Figure 2. HLS Component Synthesis Sources

The C Synthesis sources displays currently added source files, and lets you edit, or delete current source files, add new source files, and add or modify CFLAGS and CSIMFLAGS.

• Add item: Select this command to add new source files to the HLS component. This opens a File Browser, and lets you navigate to and select source files to add.
• Add CFLAGS or CSIMFLAGS: You can add compilation flags for synthesis (CFLAGS) and for simulation (CSIMFLAGS) to be applied to all source files, or to be added to specific source files. As shown in the preceding figure, simply add the flags to the appropriate text entry box for Flags common to all files. To add flags for specific source files, select the source file and select Edit item to add the flags, or modify the file name and path.
• top: Lets you specify the function to use as the top-level RTL module for synthesis. The top-level module determines the RTL ports that will be added, and which sub-functions to include in the HLS component. This opens the Select Top Function dialog box that displays a list of functions defined in the source files for you to choose the top function.

[HLS]
syn.file=<path/to/file.cpp>
syn.file_cflags=<path/to/file.cpp>,<cflag>
syn.file_csimflags=<path/to/file.cpp>,<csimflag>
syn.cflags=<cflag for all files>
syn.csimflags=<csimflag for all files>
syn.top=<top function name>

Configuring Default Settings

For the HLS component, the Vitis unified IDE offers a variety of commands that can be used to configure the default settings of the tool for synthesis and simulation. These configuration commands are presented in Config Editor under the heading of C Synthesis as shown in the figure below. Generally these options are documented as presented in the figure, such as Compile Options, Interface Configuration, and RTL Configuration.

Figure 3. HLS Component Default Settings

Assigning Design Directives

Figure 4. HLS Component Directives

Design directives let you to customize the synthesis results for the source code. Change the directives across multiple synthesis runs to change the results or optimize your design. They can be added as HLS pragmas directly to the source code, or as HLS Optimization Directives to the configuration file for use in an HLS component. In the Config File editor you will see the various directives listed, and you can select Add Item to open the Directive editor.

[HLS]
syn.directive.dataflow=dct
syn.directive.array_partition=dct buf_2d_in type=block factor=4
syn.directive.pipeline=dct2d II=4

Run Synthesis

With the key elements of the HLS component defined in the config file you are ready to run Synthesis. Select Run from the Flow Navigator to begin Synthesis. You can track the progress of the synthesis run in the Output window. The transcript for the synthesis run will have the top function name as <component-name>::synthesis. During the synthesis process messages are transcripted to the console window, and to the vitis_hls.log file.

Figure 5. HLS Component Running Synthesis

After synthesis is complete, you should see the Synthesis finished successfully message at the end of the transcript. You will also see the Reports folder under the Run command populated as shown in the preceding figure. The reports available after synthesis are as follows:

• Summary: reports the command line used and the time stamp on the results.
• Synthesis: reports the synthesis results with information on quality of results, HW interfaces, burst transactions and more. Refer to Synthesis Summary for more information.
• Function Call Graph: Displays the HLS component after C Synthesis or C/RTL Co-simulation to show the throughput of the design in terms of latency and II as described in Function Call Graph.
• Schedule Viewer: Shows each operation and control step of the function, and the clock cycle that it executes in, as described in Schedule Viewer.
• Dataflow Viewer: Only available when the DATAFLOW pragma or directive is used in the design. This report shows the dataflow structure inferred by the tool as described inDataflow Viewer.
• Kernel Guidance: reports Guidance messages to provide design advice for the source code and synthesis results.