config_rtl - 2024.1 English

Vitis High-Level Synthesis User Guide (UG1399)

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2024.1 English


Configures various attributes of the output RTL, and the type of reset used. It also allows you to use specific identification in the RTL. By default, these options are applied to the top-level design and all RTL blocks within the design.


config_rtl [OPTIONS]


-deadlock_detection <none | sim | hw | hw_diagnosis>
Enables simulation or synthesis deadlock detection in top level RTL of exported IP/XO file. The options are as follows:
  • none : Deadlock detection disabled
  • sim : Enables deadlock detection only for simulation/emulation (default)
  • hw : Deadlock detection enabled in synthesized and simulatable RTL IP. Adds ap_local_deadlock and ap_local_block signals to the IP to enable local and global deadlock detection.
  • hw_diagnosis: Deadlock detection enabled with additional diagnosis logic in generated RTL code.
-fsm_encoding [one_hot|sequential|johnson|gray|auto|none]
Default is none. Specifies the 'fsm_encoding' RTL attribute value to guide RTL synthesis.
  • auto : Allows the RTL Synthesis tool to determine the best state machine encoding.
  • gray : Uses gray state machine encoding.
  • johnson : Uses johnson state machine encoding.
  • one_hot : Uses one_hot state machine encoding.
  • sequential : Uses sequential state machine encoding.
  • none : Disables state machine encoding, the state machine is synthesized as logic.
-fsm_safe_state [auto_safe_state|reset_state|power_on_state|default_state|none]
Default is none. Specifies the 'fsm_safe_state' RTL attribute value to guide RTL synthesis. This attribute can affect the quality of synthesis results, typically resulting in less performance with greater area.
  • auto_safe_state : Implies Hamming-3 encoding.
  • default_state : Return the state machine to the default state.
  • power_on_state : Return the state machine to the POWER_ON state.
  • reset_state : Return the state machine to the RESET state.
  • none : Attribute not added to RTL, the state machine will not include safe state logic.
-header <string>
Places the contents of file <string> at the top (as comments) of all output RTL and simulation files.
Tip: Use this option to ensure that the output RTL files contain user specified identification.
Add top level event and stall ports required by kernel profiling.
Specifies the top level function name as the prefix value. This option is ignored if config_rtl -module_prefix is also specified. This is enabled by default.
-module_prefix <string>
Specifies a user-defined prefix to be added to all RTL entity/module names.
Enable keep attribute.
Register all I/O signals by default. The default is false. This is enabled when the option is specified.
-register_reset_num <int>
Specifies the number of registers to add to the reset signal. In the Vivado IP flow the default is 0. For the Vitis kernel flow, the default value is 3.
-reset [none | control | state | all]
Variables initialized in the C/C++ code are always initialized to the same value in the RTL and therefore in the bitstream. This initialization is performed only at power-on. It is not repeated when a reset is applied to the design.

The setting applied with the -reset option determines how registers and memories are reset.

No reset is added to the design.
Resets control registers, such as those used in state machines and those used to generate I/O protocol signals. This is the default setting.
Resets control registers and registers or memories derived from static or global variables in the C/C++ code. Any static or global variable initialized in the C/C++ code is reset to its initialized value.
Resets all registers and memories in the design. Any static or global variable initialized in the C/C++ code is reset to its initialized value.
Causes all registers to use a asynchronous reset. If this option is not specified, a synchronous reset is used.
-reset_level (low | high)
Allows the polarity of the reset signal to be either active-Low or active-High. The default is High.
Tip: The AXI protocol requires an active-Low reset. If your design uses AXI interfaces the tool will define this reset level with a warning if the config_rtl -reset_level is active-High.


Configures the output RTL to have all registers reset with an asynchronous active-Low reset.

config_rtl -reset all -reset_async -reset_level low

Adds the contents of my_message.txt as a comment to all RTL output files.

config_rtl -header my_mesage.txt