Clock Generation

ZCU111 Evaluation Board User Guide (UG1271)

Document ID

UG1271

Release Date

2023-04-28

Revision

1.4 English

The ZCU111 board provides fixed and variable clock sources for the XCZU28DR RFSoC. Table: Clock Sources lists the source devices for each clock.

Table 3-16: Clock Sources
Clock (Net) Name	Frequency	Clock Source
Fixed Frequency Clocks
PS_REF_CLK	33.33 MHz	U46 SI5341B clock generator
CLK_100	100 MHz
CLK_125	125 MHz
GTR_REF_CLK_SATA	125 MHz
GTR_REF_CLK_USB3	26 MHz
GTR_REF_CLK_DP	27 MHz
Programmable Frequency Clocks
USER_SI570	300 MHz (default)	U47 SI570 I2C PROG. OSC.
USER_MGT_SI570	156.25 MHz (default)	U49 SI570 I2C PROG. OSC.
USER_SMA_MGT_CLOCK	User-provided source	J14 (P)/J15 (N) SMA CONN.
SFP_SI5382_CLOCKS	Variable	U48 SI5382A clock recovery

Table 3-17: Clock Connections to XCZU28DR U1
Clock Source Ref. Des. and Pin	Net Name	I/O Standard	XCZU28DR (U1) Pin
U46 SI5341B Clock Generator
U46.59	PS_REF_CLK (series R310)	⁽¹⁾	AC30
U46.45	CLK_125_P	LVDS	AL17
U46.44	CLK_125_N	LVDS	AM17
U46.42	CLK_100_P	LVDS	AM15
U46.41	CLK_100_N	LVDS	AN15
U46.35	GTR_REF_CLK_SATA_P	⁽²⁾	AC34
U46.34	GTR_REF_CLK_SATA_N	⁽²⁾	AC35
U46.31	GTR_REF_CLK_USB3_P	⁽²⁾	AE34
U46.30	GTR_REF_CLK_USB3_N	⁽²⁾	AE35
U46.24	GTR_REF_CLK_DP_P	⁽²⁾	AG34
U46.23	GTR_REF_CLK_DP_N	⁽²⁾	AG35
U47 SI570 I2C Prog. Oscillator (300 MHz default)
U47.4	USER_SI570_P	LVDS	J19
U47.5	USER_SI570_N	LVDS	J18
U49 SI570 I2C Prog. Oscillator (156.250 MHz default)
U49.4	USER_MGT_SI570_P	⁽²⁾	V31
U49.5	USER_MGT_SI570_N	⁽²⁾	V32
J14 (P)/J15 (N) SMA Connectors
J14	USER_SMA_MGT_CLOCK_P	⁽²⁾	T31
J15	USER_SMA_MGT_CLOCK_N	⁽²⁾	T32
U48 SI5382A Clock Recovery
U48.1	SFP_SI5382_IN1_P	⁽²⁾	AA33
U48.2	SFP_SI5382_IN1_N	⁽²⁾	AA34
U48.21	SFP_SI5382_OUT_P	⁽²⁾	Y31
U48.20	SFP_SI5382_OUT_N	⁽²⁾	Y32
U48.63	SFP_REC_CLOCK_P	LVDS ⁽³⁾	AW14
U48.64	SFP_REC_CLOCK_N	LVDS ⁽³⁾	AW13
U90 LMK04208 Programmable Jitter Cleaner
U90.4	SYSREF_FPGA_C_P	LVPECL ⁽³⁾	AK17
U90.3	SYSREF_FPGA_C_N	LVPECL ⁽³⁾	AK16
U90.13	SYSREF_RFSOC_C_P	LVPECL ⁽³⁾	U5
U90.12	SYSREF_RFSOC_C_N	LVPECL ⁽³⁾	U4
U90.22	FPGA_REFCLK_OUT_C_P	LVPECL ⁽³⁾	AL16
U90.21	FPGA_REFCLK_OUT_C_N	LVPECL ⁽³⁾	AL15
Notes: 1. U1 XCZU28DR bank 503 supports LVCMOS18 level inputs. 2. Series capacitor coupled, U1 MGT (I/O standards do not apply). 3. Series capacitor coupled.