Table: MIO Peripheral Mapping
provides PS MIO peripheral mapping implemented on the ZCU111 board. See the
Zynq UltraScale+ Device Technical Reference Manual
(UG1085)
[Ref 3]
for more information on PS MIO peripheral mapping.
Table 3-2:
MIO Peripheral Mapping
|
MIO[0:25] Bank 500
|
MIO[26:51] Bank 501
|
MIO[52:77] Bank 502
|
|
0
|
QSPI
|
26
|
PMU IN
|
52
|
USB0
|
|
1
|
QSPI
|
27
|
DPAUX
|
53
|
USB0
|
|
2
|
QSPI
|
28
|
DPAUX
|
54
|
USB0
|
|
3
|
QSPI
|
29
|
DPAUX
|
55
|
USB0
|
|
4
|
QSPI
|
30
|
DPAUX
|
56
|
USB0
|
|
5
|
QSPI
|
31
|
Not assigned/no connect
|
57
|
USB0
|
|
6
|
Not assigned/no connect
|
32
|
PMU OUT
|
58
|
USB0
|
|
7
|
QSPI
|
33
|
PMU OUT
|
59
|
USB0
|
|
8
|
QSPI
|
34
|
PMU OUT
|
60
|
USB0
|
|
9
|
QSPI
|
35
|
PMU OUT
|
61
|
USB0
|
|
10
|
QSPI
|
36
|
PMU OUT
|
62
|
USB0
|
|
11
|
QSPI
|
37
|
PMU OUT
|
63
|
USB0
|
|
12
|
QSPI
|
38
|
GPIO
|
64
|
GEM3
|
|
13
|
GPIO
|
39
|
SD1
|
65
|
GEM3
|
|
14
|
I2C0
|
40
|
SD1
|
66
|
GEM3
|
|
15
|
I2C0
|
41
|
SD1
|
67
|
GEM3
|
|
16
|
I2C1
|
42
|
SD1
|
68
|
GEM3
|
|
17
|
I2C1
|
43
|
Not assigned/no connect
|
69
|
GEM3
|
|
18
|
UART0
|
44
|
Not assigned/no connect
|
70
|
GEM3
|
|
19
|
UART0
|
45
|
SD1
|
71
|
GEM3
|
|
20
|
Not assigned/no connect
|
46
|
SD1
|
72
|
GEM3
|
|
21
|
Not assigned/no connect
|
46
|
SD1
|
73
|
GEM3
|
|
22
|
GPIO
|
48
|
SD1
|
74
|
GEM3
|
|
23
|
GPIO
|
49
|
SD1
|
75
|
GEM3
|
|
24
|
Not assigned/no connect
|
50
|
SD1
|
76
|
MDI03
|
|
25
|
Not assigned/no connect
|
51
|
SD1
|
77
|
MDI03
|