User PMOD GPIO Connectors

ZCU111 Evaluation Board User Guide (UG1271)

Document ID

UG1271

Release Date

2023-04-28

Revision

1.4 English

[ This Figure , callout 20, 21]

The ZCU111 evaluation board supports two right-angle PMOD GPIO receptacles J48 and J49. The 3.3V PMOD nets are level-shifted and are wired to the XCZU28DR device U1 banks 28, 66, and 68. This Figure shows the GPIO PMOD connector circuits.

Figure 3-24: PMOD Connectors
X-Ref Target - Figure 3-24

Table: PMOD Connections to XCZU28DR lists the connections between the XCZU28DR RFSoC and the PMOD

Table 3-23: PMOD Connections to XCZU28DR
XCZU28DR (U1) Pin	Net Name ⁽¹⁾	I/O Standard	PMOD Pin
C17	PMOD0_0	LVCMOS12	J48.1
M18	PMOD0_1	LVCMOS12	J48.3
H16	PMOD0_2	LVCMOS12	J48.5
H17	PMOD0_3	LVCMOS12	J48.7
J16	PMOD0_4	LVCMOS12	J48.2
K16	PMOD0_5	LVCMOS12	J48.4
H15	PMOD0_6	LVCMOS12	J48.6
J15	PMOD0_7	LVCMOS12	J48.8
L14	PMOD1_0	LVCMOS12	J49.1
L15	PMOD1_1	LVCMOS12	J49.3
M13	PMOD1_2	LVCMOS12	J49.5
N13	PMOD1_3	LVCMOS12	J49.7
M15	PMOD1_4	LVCMOS12	J49.2
N15	PMOD1_5	LVCMOS12	J49.4
M14	PMOD1_6	LVCMOS12	J49.6
N14	PMOD1_7	LVCMOS12	J49.8
Notes: 1. Level-shifted net names at XCZU28DR have _LS appended.

For more information on the PMOD interface, see the Digilent website [Ref 28] .