PS-Side: GTR Transceivers

ZCU111 Evaluation Board User Guide (UG1271)

Document ID
Release Date
1.4 English

[ This Figure , callout 1]

The PS-side GTR transceiver bank 505 supports two DisplayPort transmit channels, USB (3.0) and SATA, as shown in This Figure .

Figure 3-30: PS-GTR Lane Assignments

X-Ref Target - Figure 3-30


Bank 505 DP (DisplayPort) lanes 0 and 1 TX support the 2-channel source only PS-side DisplayPort circuitry described in DPAUX (MIO 27-30) .

Bank 505 USB0 lane 2 supports the USB3.0 interface described in USB 3.0 Transceiver and USB 2.0 ULPI PHY .

Bank 505 SATA1 lane 3 supports the M.2 SATA connector U170 as shown in This Figure .

Bank 505 reference clocks are connected to the U46 SI5341B clock generator as detailed in SI5341B 10 Independent Output Any-Frequency Clock Generator .

Bank 505 connections are referenced in Design Constraints .