Understanding IEEE 1735 Structural Elements - 2024.1 English

Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)

Document ID
UG1118
Release Date
2024-06-19
Version
2024.1 English

The basic regions in a design protected with IEEE-1735-2014 V2 are, as follows:

Definition area
The IP author determines which tool vendors to support, and what access rights to grant to all tools, or to a specific tool. Most of the definition area remains in plain-text, even after encryption, because there are basic formatting instructions that the design tools need to properly decrypt the encrypted data.
Encrypted Key Definition
Contains the encryption keys for tool vendors supported by the IP.

Although technically part of the Definition area above, the key definition must, itself, be encrypted by the encryption tool to ensure that only authorized vendors can access the key and decrypt the encrypted payload.

Encrypted payload
The encrypted IP Verilog, SystemVerilog, or VHDL source code.
Plain-text payload
An unencrypted portion of the IP source-code. Within a single RTL source file, some content can be encrypted, and other content can be unencrypted. You do not need to encrypt the whole design file.
Important: In keeping with 1735 recommendations, Vivado handles encryption at the granularity of the module or entity and architecture pair.

The following sections define different sections of the definition area, and related pragmas that must be defined in the IP source code to support encryption. The examples are written in VHDL form. The Verilog and SystemVerilog syntax is the same except the `pragma protect keywords in Verilog replaces the `protect keyword in VHDL.