Creating a New AXI4 Peripheral - 2024.1 English

Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)

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2024.1 English

To create a new AXI4 peripheral, from the Create Peripheral, Package IP or Package a Block Design page, select Create a new AXI4 peripheral, and click Next.

  1. Enter the IP peripheral details:
    The name of the IP.
    IP version that reflects the <major#.minor#.Rev#> version scheme.
    Display name
    The name of the IP that shows in the IP catalog.
    You can have different names in the Name and Display name fields, however, the Display name must be intuitive enough that any change in Name can reflect automatically in the Display Name.
    The IP description to share with an end-user of the IP.
    IP location
    IP packager automatically adds the IP repository location.
    Overwrite existing
    Check this box to override an existing repository.
  2. Click Next.
  3. Add interfaces to your IP, based on the functionality and the required AXI type, shown in the following figure.

  4. To include interrupts to be available in your IP, select the Enable Interrupt Support option. The previous figure shows that generated IP supports edge or level interrupt (generated locally on the counter) and those interrupts can be extended to input ports by user and IRQ output.
    Add an interface using the Add button .
    Delete an interface using the Remove button .

    The data width and the number of registers vary, based upon the AXI4 selection type.

  5. Click Next, and review your selections.

    The details of your IP are listed in the final wizard page.

  6. Using the following Next Steps options after you create the peripheral IP:
    Add IP to the repository
    Lets you add IP to the IP repository.
    Edit IP
    Lets you edit the IP.
    Verify Peripheral IP using AXI4 VIP
    Lets you see an AXI4 VIP Simulation demonstration design and verify your IP using the AXI4 VIP.
    Verify peripheral IP using JTAG interface
    Creates a block design with which you can debug your IP module in hardware for a system with JTAG-to-AXI IP. See the Vivado Design Suite User Guide: Programming and Debugging (UG908) for more information about the Vivado debug tools.

You can generate a bitstream and validate the register writes and reads (from the sample Tcl script generated by the tool for your design) in the debug mode after the targeted device is programmed. You can do so by connecting to the board server from hardware manager, programming the board, and sourcing the Tcl script. See the Vivado Design Suite User Guide: Using Tcl Scripting (UG894) for more information.

After you create the peripheral, you have the option to add custom logic and make the peripheral a custom IP.

See the Vivado Design Suite Tutorial: Creating, Packaging Custom IP (UG1119) for a demonstration. When this step completes, review the packaging steps shown in the Package IP window in Packaging IP.