Top-Level HDL Requirements - 2024.1 English

Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)

Document ID
UG1118
Release Date
2024-06-19
Version
2024.1 English

The IP packager supports HDL synthesis language constructs for the top-level HDL file of the IP. Following these requirements ensures proper functionality of your custom IP.

  • The IP packager supports Verilog and VHDL as a top-level.
Important: If you have a SystemVerilog or VHDL-2008 as a top-level design file, create a Verilog or VHDL wrapper file prior to packaging.
  • The supported SystemVerilog constructs are the same as those supported in AMD synthesis. For a list of supported SystemVerilog constructs, see Vivado Design Suite User Guide: Synthesis (UG901).
  • All IP used within the Vivado IP catalog support multi-language usage, which allows the end user to generate an HDL wrapper for a language different than your IP.
  • To avoid conflicts, avoid using HDL language keywords within the design.
  • To ensure that the custom IP simulates properly when using VHDL, set the top-level ports to be std_logic or std_logic_vector.

Regardless of the top-level port type, when you synthesize the IP out-of-context (OOC), the resulting IP netlist ports are converted to std_logic or std_logic_vector. The converted netlist ports could cause type mismatch issues with RTL simulation.

For Verilog, module declarations with complex or split ports are not supported.

As an example, the following module declaration contains unsupported complex and split port types:

module top({in1, in2}, out[0], out[1]); 
  input	in1, in2;
  output [1:0] out; 
endmodule