Processing Order of Constraints - 2024.1 English

Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)

Document ID
UG1118
Release Date
2024-05-30
Version
2024.1 English

The Vivado IP that deliver constraints are processed either before or after you design constraints. For more information on using constraints, see the Vivado Design Suite User Guide: Using Constraints (UG903).

Important: An XDC marked as OUT_OF_CONTEXT is processed before all other XDC files used in the IP, including those marked to have a PROCESSING_ORDER value of EARLY. The default value of PROCESSING_ORDER is NORMAL. There is also a LATE value.

When creating your custom IP, you must determine the order in which the constraints are processed in the context of your design. The IP packager inherits the processing order set on the constraint files in the project. Set these properties properly in your project prior to packaging the IP. The constraints delivered for an IP only support two processing orders: EARLY and LATE. All constraints marked as the default of NORMAL are converted to EARLY.

By default, top-level user constraints have the processing order set to NORMAL, which comes between EARLY and LATE. This way an IP can provide output clocks that the top-level reference in an EARLY XDC and allows for the top-level constraints to override an IP constraint if needed.

If an IP constraint has a dependency to a top-level constraint, such as a top-level clock object, place the constraint in an XDC marked as LATE. This ensures that the required object is present when the IP constraint is processed. In the case of the IP being synthesized out-of-context, the OOC XDC provides the top-level clock object.

Note: AMD IP XDC files that have their PROCESSING_ORDER property set to LATE are named <IP_NAME>_clocks.xdc. This naming convention is not required for a custom IP.

Most constraints for an IP belong in the EARLY processing order. The constraints marked for LATE require user constraints prior to processing. This generally refers to clock dependencies.