Standard File Groups - 2024.1 English

Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)

Document ID
UG1118
Release Date
2024-05-30
Version
2024.1 English

The following table lists the Standard file group types and a description.

Table 1. Standard File Group Types and Descriptions
Standard File Groups
Examples Files that make up an example. Typically contains a constraint (XDC), HDL, and/or XIT files. Vivado uses these files to seed a new Vivado example project and shows this to the end-user for their exploration. The files are available for both synthesis and simulation.
Product Guide The production guide for an IP.
Readme Any required readme.txt file.
Simulation Simulation files to deliver. Use when you have a mix of VHDL and Verilog to simulate together. Typically, the sources are exclusive of €œVHDL Simulation€ and/or €œVerilog Simulation.€ The files could be the same as the files in the corresponding synthesis file group (when the synthesis files can also be used for simulation) or could be different (when a behavioral simulation model files are to be used).
Synthesis Synthesis files to deliver. Use when you have a mix of VHDL and Verilog to synthesize to together. Typically exclusive of œVHDL Synthesis€ and €œVerilog Synthesis.€ Adding a constraint (XDC) file here causes the constraint file to be applied to the top-level of the IP during implementation.
Verilog Simulation Simulation files to deliver. Use when you have a Verilog only representation to simulate. You might see both this file group and €VHDL Simulation€ to allow the ability to have a language-specific IP simulation. The files could be the same as the files in the corresponding synthesis file group (when the synthesis files can also be used for simulation) or might be completely different (when a behavioral simulation model files are to be used).
Verilog Synthesis Synthesis files to deliver. Use when you have a Verilog-only representation to synthesize. You might see both this file group and €œVHDL Synthesis€ to allow the ability to have a language specific implementation of the IP. Adding a constraint (XDC) file here applies the constraint file to the top-level of the IP during implementation.
Note: Synthesis run files are not stored in the IP packager.
VHDL Simulation Simulation files to deliver. Use when you have a VHDL only representation to simulate. You might see both this file group and €œVerilog Simulation€ to allow the ability to have a language specific IP simulation. The files could be the same as the files in the corresponding synthesis file group (when the synthesis files can also be used for simulation) or might be completely different (when a behavioral simulation model files are to be used).
VHDL Synthesis Synthesis files to deliver. Use when you have a VHDL only representation to synthesize. You might see both this file group and €Verilog Synthesis€ to allow the ability to have a language specific implementation of the IP. Adding a constraint (XDC) file here causes the constraint file to be applied to the top-level of the IP during implementation.