Packaging a Design with Global Include Files - 2024.1 English

Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)

Document ID
UG1118
Release Date
2024-06-19
Version
2024.1 English

The Vivado IDE supports designating Verilog or Verilog Header files as global `include files to process before any other sources.

Note: This feature is not supported when packaging a custom IP.

After packaging, the Vivado tool treats global `include files as standard Verilog or Verilog Header files.

To package a design that uses global `include files, you must modify the HDL to place the `include statement at the top of any Verilog source file that references content from another Verilog or Verilog header file.