The Vivado IDE supports designating Verilog or Verilog Header files as global
`include
files to process before any other sources.
- In VHDL, package files are used for sharing common code across various source files.
- Use work.package_pack.all; can be used in headers to include package files.
- IS_GLOBAL_INCLUDE is checked in the properties window after selecting the package_pack.vhd generally to avoid errors.
Note: This feature is not supported when packaging a custom IP.
After packaging, the Vivado tool treats global `include
files as standard Verilog or Verilog Header files.
To package a design that uses global `include
files, you must modify the HDL to
place the `include
statement at the top of any Verilog source file that
references content from another Verilog or Verilog header file.