The Vivado IP packager can automatically infer interfaces for clock and reset signals for your IP. This helps the use of custom IP in the IP integrator for validating clock and reset signals within the block diagram. There is a required nomenclature to properly infer clock and reset interfaces. If the reset signal does not contain the required nomenclature, you can manually create the interface and set the properties accordingly.
The following list describes how the reset is inferred based upon the naming of the signal.
-
[*_]aresetn -
[*_]axi_resetn -
[*_]reset[_*] -
[*_]resetin -
[*_]resetn -
[*_]rst -
[*_]rst_n -
[*_]rstin -
[*_]rstn
For reset signals that end with n
such as resetn and aresetn, which implies an active-Low signal, the interface automatically
sets the polarity parameter to active_Low. This
parameter is used in the Vivado IP integrator to
determine if the reset is properly connected when the block diagram is generated. For
all other reset interfaces, the POLARITY parameter is not set, and is determined through
the parameter propagation feature of IP integrator. For more information on parameter
propagation and IP integrator, see the
Vivado Design Suite User Guide: Designing
IP Subsystems Using IP Integrator (UG994).