Resets - 2.4 English

Video Processing Subsystem Product Guide (PG231)

Document ID
Release Date
2.4 English

The aresetn_ctrl signal is the active-Low reset input signal of the IP. The reset signal must be synchronous to the aclk_ctrl signal. Each time this reset is asserted, it should be asserted for a minimum of 16 clock cycles of the slowest clock. All registers are reset to power-on conditions; all queues are flushed; all internal logic returned to power-on conditions.

The aresetn_io_axis signal is an outgoing signal that can be used to hold IPs in reset when the Video Processing Subsystem is not ready to consume data on the streaming input. This reset signal is synchronous to the aclk_axis signal.

For Full-fledged and Scaler Only modes along with aresetn_ctrl signal, there is an internal gpio reset signal to reset the sub cores of vpss. To control the internal gpio, you have to get the internal gpio configuration, where you can set/reset the IP.