AXI-MM Memory-Mapped Interface - 2.4 English

Video Processing Subsystem Product Guide (PG231)

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2.4 English

The video DMA read and write ports and the deinterlacer read and write ports are concentrated by an AXI4 cross-bar interconnect such that there is only one AXI4 interface on the boundary of the subsystem. The AXI4 interface runs on the aclk_axi_mm clock domain. The signals follow the specification as defined in the Vivado Design Suite: AXI Reference Guide (UG1037).

The AXI4 interface is only present with the Full Fledged functionality and Deinterlacer Only configurations. The other configurations do not require access to eternal memory.

For full fledged mode, when the Built-in DMA is enabled, the MM interface data-width can be either of 128, 256 or 512 bits. Data-width is automatically configured based on the PPC of the design.