This section contains information about constraining the core in the Vivado Design Suite.
Required Constraints
The only constraints required are clock frequency constraints for the AXI4-Stream video
interfaces clock, aclk_axis, AXI4-Lite control interface clock,
aclk_ctrl, and memory subsystem clock, aclk_axi_mm.
Paths from AXI4-Lite signals should be constrained with a set_false_path,
causing setup and hold checks to be ignored for AXI4-Lite signals. These constraints are
provided in the XDC constraints files included with the IP.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP subsystem.
Clock Frequencies
This section is not applicable for this IP subsystem.
Clock Management
This section is not applicable for this IP subsystem.
Clock Placement
This section is not applicable for this IP subsystem.
Banking
This section is not applicable for this IP subsystem.
Transceiver Placement
This section is not applicable for this IP subsystem.
I/O Standard and Placement
This section is not applicable for this IP subsystem.