The Video Processing Subsystem has the following features:
- One, two, four, and eight pixel-wide video interface
- If deinterlacer is enabled in the data pipeline, then the overall processing subsystem gives 1 sample per clock equivalent performance
- Runtime color space support for RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0
- 8, 10, 12, and 16 bits per component support
- Deinterlacing: supports 32-bit and 64-bit memory address
- Scaling
- Color space conversion and correction
- Chroma resampling between YUV 4:4:4, YUV 4:2:2, YUV 4:2:0
- Frame rate conversion
- Supports resolutions up to 8192 x 4320
The Video Processing Subsystem is a hierarchical IP that bundles a collection of video processing IP subcores and outputs them as a single IP. The Video Processing Subsystem has design time configurability in terms of performance and quality. You can configure the subsystem IP through one single graphical user interface. A preview of this GUI is shown in Figure 1.
All video processing IP subcores are developed using AMD Vitis™ HLS.