Full fledged mode uses all the register maps of deinterlacer only, scaler only,
420-422 chroma resampling, and 422-444 chroma resampling only registers mentioned above.
Letterbox is also included in full fledge mode. In this Full Fledged mode there are two
AXI GPIO IPs in the VPSS. One AXI GPIO, that is, reset_sel_axis is configured with width 2. This resets the subcores like
v_csc, v_vcresampler, v_hcresampler, v_letterbox, v_hscaler,
and v_vscaler through the upper bit of its 2-bit width
output and the lower bit of its 2-bit output is connected to the VPSS output signal,
that is, arestn_io_axis[0:0]. The second AXI GPIO, that
is, reset_sel_axi_mm is configured with width 1 to
reset the v_deinterlacer and VDMA IPs.
For more information, see AXI GPIO LogiCORE IP Product Guide (PG144).