Clocks and Resets - 2.4 English

Video Processing Subsystem Product Guide (PG231)

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2.4 English

The following table provides an overview of the clocks and resets. See section Clocking for more information.

Table 1. Clocks and Resets
Name Direction Width Description
aclk_axis In 1 Clock at which AXI4-Stream input and output are running.
aclk_ctrl In 1 AXI4-Lite clock for CPU control interface.
aclk_axi_mm In 1 Clock at which AXI4 interface is running.
aresetn_ctrl In 1 Reset, associated with aclk_ctrl (active-Low). The aresetn_ctrl signal resets the entire IP including the data path and AXI4-Lite registers.
aresetn_io_axis Out 1 Used to hold upstream logic in reset while the Video Processing Subsystem is not ready to consume data on streaming input (active-Low).