Port Descriptions - 2.4 English

Video Processing Subsystem Product Guide (PG231)

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2.4 English

The following figure shows the Video Processing Subsystem diagram in its Full Fledged configuration. The IP has four AXI interfaces:

  • AXI4-Stream streaming video input (s_axis)
  • AXI4-Stream streaming video output (m_axis)
  • AXI-MM memory mapped interface (m_axi_mm)
  • AXI-Lite control interface (s_axi_ctrl).
Figure 1. Full Fledged Video Processing Subsystem

The AXI Streaming, AXI Memory-Mapped, and AXI Lite interfaces can be run at their own clock rate, therefore, three separate clock interfaces are provided named aclk_axis, aclk_axi_mm, and aclk_ctrl, respectively. The aresetn_ctrl signal is the reset signal of the IP, and aresetn_io_axis is an outgoing signal that can be used to hold IPs in reset when the Video Processing Subsystem is not ready to consume data on the streaming input. Finally, deint_field_id signal indicates field polarity in case of interlaced operation.