The input DATA and output DATA channels share
a common tdata structure format, though can have
different bit widths. All parallel data paths (See Parallel Data Channel Filters) and parallel data samples (See Super Sample Rate Filters) are contained in the tdata bus, with each path being sign extended to an 8-bit boundary. The
extra bits on the input tdata are not used by the
core.
The following figure shows the tdata structure for a case with 2 parallel paths (data
streams). In this case, bit growth is experienced between input and output—a path width
of 11 bits on the input grows to 13 bits on the output.
Figure 1. Tdata Structure for Input and Output DATA Channels
Note: The AXI4-Port
Structure pane on the Implementation Details Tab of the customization GUI displays the
bus structure of all AXI channels for the specified configuration.