Feature Support Matrix - 7.2 English - PG149

FIR Compiler LogiCORE IP Product Guide ( PG149)
Document ID
PG149
Release Date
2025-06-11
Version
7.2 English
Table 1. Feature Support Matrix
Feature Systolic Multiply-Accumulate Transpose Multiply-Accumulate
Number of Coefficients(1) 2–2048 2–2048
Coefficient Width (2) 2–49 2–49
Data Width(2)(4) 2–49 2–49
Number of Interleaved Channels 1–1024(5) 1
Number of Parallel Data Channels(4) 1-16 1-16

Maximum Rate Change

  • Single Channel
  • Multiple Channels

1024

512

1024

N/A
Fractional Rate Support Yes No
Coefficient Reload(6) Yes Yes
Coefficient Sets 1–256 1–256
Output Rounding Yes Yes
Super Sample Rate(7) Yes No
  1. The upper limit on the number of coefficients exists only when the FIR Compiler is configured with more than one coefficient set.
  2. Maximum Coefficient Width reduces by one when the Coefficients are signed. Similarly for Maximum Data Width when the Data values are signed.
  3. The allowable range for the Data Width field in the Vivado IDE might reduce further to ensure that the accumulator width does not exceed the maximum.
  4. Maximum Parallel Datapaths reduces to 8 when Coefficient Width or Data Width is greater than 25-bits.
  5. Continuous 1 to 256, plus 512 and 1024.
  6. Coefficient Reload is not supported with fractional rate interpolation filter when configured for super sample rate.
  7. Sample frequency greater than clock frequency.

The following table shows the classes of filters that are supported for the FIR Compiler core.

Table 2. Filter Configuration Support Matrix
Filter Configuration Supported
Conventional Single-rate FIR Yes
Half-band FIR Yes
Hilbert Transform [Ref 1] Yes
Interpolated FIR [Ref 2] [Ref 5] Yes
Polyphase Decimator Yes
Polyphase Interpolator Yes
Half-band Decimator Yes
Half-band Interpolator Yes

The supported filter configurations are described in separate sections within this document.