Interleaved Channel Specification
- Channel Sequence
- This field selects between Basic and Advanced interleaved data channel sequences. The Basic implementation processes interleaved data channels starting at channel 0 incrementing in steps of 1 to Number of Channels - 1. The Advanced implementation can processes interleaved data channels in multiple predefined sequences. The desired sequences are specified using the Sequence ID List parameter. The CONFIG channel is used to select the active channel sequence. See Interleaved Data Channel Filters for more details.
- Number of Channels
- The maximum number of interleaved data channels to be processed by the filter. For Advanced channel sequences this parameter specifies the channel sequence length, which also specifies the maximum number of interleave data channels.
- Select Sequence
- This field can be used to select which of the supported channel sequences are to be implemented. Selecting All populates the Sequence ID List with all the available channel sequences. Similarly, Clear All removes all the sequences apart from default first channel sequence supported. Selecting a specific channel sequence toggles its entry in the Sequence ID List parameter.
- Sequence ID List
- A comma delimited list that specifies which channel sequences are implemented by the core. The Interleaved Channel Pattern pane of Implementation Tab, Implementation, displays the enumerated list of selected patterns. The Select Sequence parameter can be used to populate the list. See Interleaved Data Channel Filters for details of the supported channel sequences.
Parallel Channel Specification
- Number of Paths
- Specifies the number of parallel datapaths the filter is to process. Each parallel datapath is extended to a byte boundary, for both the input and output widths selected. The padding can be signed extended or set to zero.
Hardware Oversampling Specification
- Select Format
- Selects which format is used to specify the hardware oversampling rate, the number of clock cycles available to the core to process an input sample and generate an output. This value directly affects the level of parallelism in the core implementation and resources used. When Frequency Specification is selected, you can specify the Input Sampling Frequency and Clock Frequency. The ratio between these values along with other core parameters determine the hardware oversampling rate. When Input Sample Period is selected, you can specify the number of clock cycles between input samples. Similarly, when Output Sample Period is selected, you can specify the number of clock cycles between output samples.
- Sample Period
- Number of clock cycles between input or output samples. When the multiple channels have been specified, this value should be the integer number of clock cycles between the time division multiplexed input sample data stream. A sample frequency greater than the clock frequency can be specified using a fractional sample period (see Super Sample Rate Filters).
- Input Sampling Frequency
- This field can be an integer or real value; it specifies the sample
frequency for one channel. The upper limit is set based on the clock
frequency and filter parameters such as Interpolation Rate and number of
channels.Note: When using the Advanced Interleaved Data Channel Filters (see Interleaved Data Channel Filters), the Input Sample Frequency is specified for the highest frequency channel (fs) supported by the selected advanced channel configuration. For N channels, this is the sample frequency of PN-0, as seen in Advanced Interleaved Data Channel Patterns.
- Clock Frequency
- This field can be an integer or real value. The limits are set based on the sample frequency, interpolation rate, and number of channels. This field influences architecture choices only; the specified clock rate might not be achievable by the final implementation.