The half-band decimator is a polyphase filter with an embedded 2-to-1 down-sampling of the input signal. This Figure shows the structure.
The filter is very similar to the polyphase decimator described in Polyphase Decimator with the decimation factor set to M =2. However, there is a subtle difference in the implementation that makes the half-band decimator a more area-efficient 2-to-1 down-sampling filter when the frequency response reflects a true half-band characteristic.
The frequency and time response of a half-band filter are shown in
This Figure
and
This Figure
, respectively. Observe the alternating zero-valued coefficients in the impulse response.
This Figure
details a 7-tap half-band polyphase filter when the coefficients are allocated to the two polyphase segments
and
shown in
This Figure
.
This Figure
(a) is the filter impulse response (
).
This Figure
(b) provides a detailed illustration of the polyphase subfilters and shows how the filter coefficients are allocated to the two polyphase arms.
In the bottom arm,
the only non-zero coefficient, is the center value of the impulse response
This Figure
(c) shows the optimized architecture when the redundant multipliers and adders are removed and coefficient symmetry is exploited. The final structure has a reduced computation workload in contrast to a more general 2:1 down-sampling filter.
The number of multiply-accumulate (MAC) operations required to compute an output sample has been lowered by a factor of approximately two. In this figure, the high density of zero-valued filter coefficients is exploited in the FPGA realization to produce a minimal area implementation.
