The aresetn
port is an optional active-Low input port which, when asserted for a minimum of two
cycles, forces the internal control logic to the initialized condition and optionally
clears the data vector of the core. Selecting the data vector reset results in the core
using more FPGA logic resources.
When the data vector reset is disabled, no
internal data is cleared from the filter memories during the reset process. The filter
output remains dependent on the prior input samples. The data_valid field of the m_axis_data_tuser bus (see TUSER Options) indicates when the filter data memory is completely
flushed and can be used as additional qualification of the m_axis_data_tdata bus.
When you enable the Blank Output option, the
filter output is forced to zero until the data_valid
field of m_axis_data_tuser is set (the filter output
can be generated from a complete data vector).
When using RELOAD Channel:
- Coefficient vector reset disabled
- Reset clears only the RELOAD channel control logic; the coefficient data is preserved and remains pending for application. As a result, it is possible to clear the data vector after new coefficients are loaded but before they are applied to coefficient memory through a Synchronization Event (see CONFIG Channel).
- Coefficient vector reset enabled
- Reset clears both the control logic and coefficient data, allowing loaded coefficients to be discarded before application through a Synchronization Event (see CONFIG Channel).