The aresetn port is an
optional active-Low input port which, when asserted for a minimum of two cycles, forces
the internal control logic to the initialized condition and optionally clears the data
vector of the core. Selecting data vector reset can result in the core using more FPGA
logic resources.
When data vector reset has not been selected no
internal data is cleared from the filter memories during the reset process. The filter
output remains dependent on the prior input samples. The data_valid field of the m_axis_data_tuser bus, see TUSER Options, indicates when the filter data memory has been
completely flushed and can be used as additional qualification of the m_axis_data_tdata bus. When the Blank
Output option is selected, the filter output is forced to zero until the
data_valid field of m_axis_data_tuser is set (the filter output can be generated from a
complete data vector).
When using the RELOAD Channel, no coefficient data is cleared upon reset; only the control logic of the RELOAD channel is reset. As a result, it is possible to clear the data vector after new coefficients have been loaded, but before they have been applied to coefficient memory through a Synchronization Event (see CONFIG Channel).