Demonstration Test Bench - 7.2 English

FIR Compiler (PG149)

Document ID
PG149
Release Date
2022-10-26
Version
7.2 English

When the core is generated using the Vivado IP catalog, a demonstration test bench is optionally created. This is a simple VHDL test bench that exercises the core.

The demonstration test bench source code is one VHDL file: demo_tb/tb_<component_name>.vhd in the Vivado Design Suite output directory. The source code is comprehensively commented.