• Goal : Specifies if the core is required to operate at maximum possible speed (Speed or Custom option) or minimum area (Area option).
RECOMMENDED: The Area option is the recommended default and normally achieves the best speed and area for the design.
In certain configurations, the Speed or Custom setting might be required to improve performance at the expense of overall resource usage. The Speed option selects all the possible optimizations supported by the core. The Custom option enables the Select Optimization and List parameters where individual optimizations can be specified. This provides finer control over the optimizations applied to specifically target any critical paths.
• Select Optimization : This is a helper parameter that can be used to select/deselect the entries in the Optimization List. Selecting All fully populates the list with all possible optimizations. This does the same as selecting the Speed Optimization Goal. Selecting None deselects all optimizations. Selecting a specific optimization toggles its entry in the Optimization List.
• List : Comma delimited list that specifies which optimizations are implemented by the core.
° Data_Path_Fanout : Adds additional pipeline registers on the data memory outputs to minimize fan-out. Useful when implementing large data width filters requiring multiple DSP slices per multiply-add unit.
° Pre-Adder_Pipeline : Pipelines the pre-adder when implemented using fabric resources. This may occur when a large coefficient width is specified.
° Coefficient_Fanout : Adds additional pipeline registers on the coefficient memory outputs to minimize fan-out. Useful for Parallel channels or large coefficient width filters requiring multiple DSP slices per multiply-add unit.
° Control_Path_Fanout : Adds additional pipeline registers to control logic when Parallel channels have been specified.
° Control_Column_Fanout : Adds additional pipeline registers to control logic when multiple DSP columns are required to implement the filter.
° Control_Broadcast_Fanout : Adds additional pipeline registers to control logic for fully parallel (one clock cycle per channel per input sample) symmetric filter implementations.
° Control_LUT_Pipeline : Pipelines the Look-up tables required to implement the control logic for Advanced Channel sequences.
° No_BRAM_Read_First_Mode : Specifies that Block RAM READ-FIRST mode should not be used. This can increase the achievable F Max of the core configuration.
° Optimal_Column_Lengths : Partitions the DSP slice columns to maximize speed when multiple DSP slice columns are required for non-symmetric filter implementations.
° Data_Path_Broadcast : Forces the use of a fabric-efficient implementation for single rate fully parallel symmetric filter configurations. For single channel configurations, this can result in a lower F Max for filters with a large number of taps. This structure is available only in configurations with a single DSP column, single filter set, and basic interleaved channels.
° Disable_Half_Band_Center_Tap : Disables the half-band interpolation center tap optimization. When selected, a DSP slice is used to implement the center tap. This optimization applies only to UltraScale devices.
° Other : Miscellaneous optimizations.
Note: All optimizations maybe specified but are only implemented when relevant to the core configuration.