Features - 7.2 English

FIR Compiler (PG149)

Document ID

PG149

Release Date

2022-10-26

Version

7.2 English

• AXI4-Stream-compliant interfaces

• High-performance finite impulse response (FIR), polyphase decimator, polyphase interpolator, half-band, half-band decimator and half-band interpolator, Hilbert transform and interpolated filter implementations

• Support for up to 256 sets of coefficients, with 2 to 2048 coefficients per set when handling more than one set.

• Input data up to 49-bit precision

• Filter coefficients up to 49-bit precision

• Support for up to 1024 interleaved data channels

• Support for advanced interleaved data channel sequences

• Support for multiple parallel data channels with shared control logic

• Interpolation and decimation factors of up to 64 generally and up to 1024 for single channel filters

• Support for sample frequency greater than clock frequency

• Online coefficient reload capability

• User-selectable output rounding

• Efficient multi-column structures for all filter implementations and optimizations

LogiCORE IP Facts Table
Core Specifics
Supported Device Family ⁽¹⁾	Versal ® ACAP, UltraScale+ ™ , UltraScale ™ , Zynq-7000 SoC 7 Series
Supported User Interfaces	AXI4-Stream
Resources	Performance and Resource Utilization web page
Provided with Core
Design Files	Encrypted RTL
Example Design	Not Provided
Test Bench	VHDL
Constraints File	Not Provided
Simulation Model	Encrypted VHDL
Supported S/W Driver	N/A
Tested Design Flows ⁽²⁾
Design Entry	Vivado ® Design Suite System Generator for DSP
Simulation	For supported simulators, see the Xilinx Design Tools: Release Notes Guide .
Synthesis	Vivado Synthesis
Support
Release Notes and Known Issues	Master Answer Record: 54502
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes: 1. For a complete listing of supported devices, see the Vivado IP catalog. 2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide .