Hardware Oversampling Specification - 7.2 English - PG149

FIR Compiler (PG149)

Document ID
PG149
Release Date
2022-10-26
Version
7.2 English

Select format : Selects which format is used to specify the hardware oversampling rate, the number of clock cycles available to the core to process an input sample and generate an output. This value directly affects the level of parallelism in the core implementation and resources used. When Frequency Specification is selected, you can specify the Input Sampling Frequency and Clock Frequency. The ratio between these values along with other core parameters determine the hardware oversampling rate. When Input Sample Period is selected, you can specify the number of clock cycles between input samples. Similarly, when Output Sample Period is selected, you can specify the number of clock cycles between output samples.

Sample Period : Number of clock cycles between input or output samples. When the multiple channels have been specified, this value should be the integer number of clock cycles between the time division multiplexed input sample data stream. A sample frequency greater than the clock frequency can be specified using a fractional sample period (see Super Sample Rate Filters ).

Input Sampling Frequency : This field can be an integer or real value; it specifies the sample frequency for one channel. The upper limit is set based on the clock frequency and filter parameters such as Interpolation Rate and number of channels.

Note: When using the Advanced Interleaved Data Channel Filters (see Interleaved Data Channel Filters ), the Input Sample Frequency is specified for the highest frequency channel (fs) supported by the selected advanced channel configuration. For N channels, this is the sample frequency of PN-0, as seen in Table: Advanced Interleaved Data Channel Patterns .

Clock Frequency : This field can be an integer or real value. The limits are set based on the sample frequency, interpolation rate, and number of channels. This field influences architecture choices only; the specified clock rate might not be achievable by the final implementation .