Two implementations of the associated control logic are available when the coefficient memory has been specified to use block RAM.
The core can be configured to avoid the use of the block memory READ-FIRST mode. This results in the core achieving a greater F max but requires more FPGA resources.
Alternatively, the core can use the Block RAM READ-FIRST mode and minimize the FPGA resources required at the expense of a lower F max .
The No_BRAM_Read_First_Mode Optimization option is used to select which implementation is required. This is automatically selected when the Optimization Goal is set to Speed or can be explicitly selected by using the Custom optimization goal and then selecting the No_BRAM_Read_First_Mode optimization.