Creating an HLS Component - 2023.2 English

1. With the Vitis IDE opened, from the main menu select File > New Component > HLS.

   Tip: You can also select New Component on the Welcome page, or from the right-click menu in the Explorer view.

2. This opens the Choose Name and Location page of the Create HLS Component wizard as shown below.

   Figure 1. Create HLS Component - Name and Location

   Enter a Component name and Component location and select Next.

3. This opens the Configuration File page of the wizard as shown below. The HLS component configuration file contains commands and directives used for the synthesis, simulation, and export of the component.

   Figure 2. Create HLS Component - Configuration File

   The Configuration File page of the Create HLS Component wizard provides three ways to add a configuration file to your component:

   • Empty File: Specifies the creation of a new empty configuration file to be populated after component creation as described in Defining the HLS Config File. Selecting this option lets you specify a name in the New configuration file name field.
   • Existing File: Specifies the use of an existing configuration file. Selecting this option lets you enter the path and name in the File field, or select Browse to locate the file.
   • Generate from Vitis HLS Project: This option generates a new config file from an existing Vitis HLS project hls.app file. The tool lets you identify the hls.app file inside the project, and enter a New configuration file name for the config file generated from the hls.app file.

   Choose the method of adding the config file to your HLS component, and specify a name or files as needed. Select Next to proceed to the Source Files.

4. The Source Files page of the wizard opens as shown below.

   Figure 3. Create HLS Component - Source Files

   Under Design Files you can you can select Add files to select the primary source file for the design, or add multiple files as needed. After adding one or more source files, you can identify the Top Function which is the function to be synthesized as the top-level function for the HLS component. Any functions called by the top-function will also be synthesized into RTL.

   Under Test Bench Files you can select Add files or select Add folders to add files containing test bench and associated files for the HLS component.

   For both design files and test bench files you can add CFLAGS and CSIMFLAGS to specify directives to be used during compilation and simulation. You can specify directives to be applied to all files or to specific files from each category. After adding files and folders and directives, select Next to proceed.

5. The Select Part page of the wizard is opened as shown below.

   Figure 4. Create HLS Component - Part

   Select the Part or select the Platform for the HLS component and select Next to proceed.

   Tip: If you select Platform when creating the HLS component, the Vitis unfied IDE extracts the part from the specified platform and adds part= to your configuration file.
6. This displays the Settings page of the wizard as shown below.
   
   

   The Settings page lets you specify a clock period or frequency for the design, and a clock uncertainty. The default clock for the tool is a clock period of 10 ns (or 100 MHz), and a clock uncertainty of 27% as described in Specifying the Clock Frequency.

   The Settings page also lets you specify the flow_target for the HLS component build process as being either to generate a Vivado IP or a Vitis kernel as described in Target Flow Overview. The interface requirements of the Vivado IP or a Vitis kernel are different as explained in Interfaces of the HLS Design. The default flow_target is the Vivado IP flow.

   Below the flow_target you can also specify the package.output.format for the tool to generate when packaging the design. The default output format is the Vivado IP, which generates a .zip file to be added to your IP catalog, letting you use the HLS generated RTL design in other designs.

   Note: Selecting the Vitis flow_target does not automatically change the output format to Vitis kernel. The default is still Vivado IP, but you can manually change the output format if needed.

   Also keep in mind that the HLS component uses a bottom-up design flow, generating only RTL output until you package the output as described in Packaging the RTL Design. The bottom-up flow lets you develop multiple design iterations as you sort through the design challenges, and only package the output when the design is ready. This approach saves significant time each time you run Synthesis or Simulation.

   Select Next to proceed to the Summary page.

7. The Summary page reflects the choices you have made on the prior pages. Review the summary and select Finish to create the HLS component, or select Back to return to earlier pages and change your selections.

When the HLS component is created the vitis-comp.json file for the component is opened in the central editor window, and the HLS component becomes active in the Flow Navigator as shown below.

Figure 5. HLS Component - vitis-comp.json

After creation, the HLS component becomes the active component in the Flow Navigator, or you can select the Component to make it the active component in the tool. When the HLS component is the active component, the Flow Navigator enables running C Simulation, C Synthesis, C/RTL Co-simulation, Package, and Implementation as shown in the following image.

Figure 6. HLS Component - Flow Navigator

To manage the actions of these steps however, you will need to edit the HLS config file to achieve your design objectives as described below.