User Parameters - 3.1 English

HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)
Document ID
PG236
Release Date
2020-12-11
Version
3.1 English

The following table shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console).

Table 1. Vivado IDE Parameter to User Parameter Relationship
Vivado IDE Parameter/Value User Parameter/Value Default Value
Toplevel
Video Interface
  • AXI4-Stream
  • Native Video
 C_VID_INTERFACE
  • 0
  • 1
 AXI4-Stream
Include HDCP 1.4 Decryption
  • Exclude (Untick)
  • Include (Tick)
 C_INCLUDE_HDCP_1_4
  • FALSE
  • TRUE
 Exclude
Include HDCP 2.3 Decryption
  • Exclude (Untick)
  • Include (Tick)
 C_INCLUDE_HDCP_2_2
  • FALSE
  • TRUE
 Exclude
Video over AXIS compliant NTSC/PAL Support
  • Exclude (Untick)
  • Include (Tick)
 C_INCLUDE_LOW_RESO_VID
  • FALSE
  • TRUE
 Exclude
Video over AXIS compliant YUV420 Support
  • Exclude (Untick)
  • Include (Tick)
 C_INCLUDE_YUV420_SUP
  • FALSE
  • TRUE
 Exclude
Max bits per component
  • 8
  • 10
  • 12
  • 16
 C_MAX_BITS_PER_COMPONENT
  • 8
  • 10
  • 12
  • 16
 8
Number of pixels per clock on Video Interface
  • 2
  • 4
 C_INPUT_PIXELS_PER_CLOCK
  • 2
  • 4
 2
Hot Plug Detect Active
  • High
  • Low
 C_HPD_INVERT
  • High
  • Low
 High
Cable Detect Active
  • High
  • Low
 C_CD_INVERT
  • High
  • Low
 High
EDID RAM Size
  • 256
  • 512
  • 1024
  • 4096
 C_EDID_RAM_SIZE
  • 256
  • 512
  • 1024
  • 4096
 256
Video Bridge
FIFO Depth
  • 32
  • 1024
  • 2048
  • 4096
  • 8192
 C_ADDR_WIDTH
  • 32
  • 1024
  • 2048
  • 4096
  • 8192
 1024
Example Design
Design Topology
  • Pass-Through
  • Rx Only
 C_EXDES_TOPOLOGY
  • 0
  • 2
 0
AXI4-Lite Frequency 1
  • 50
  • 100
  • 150
  • 200
 C_EXDES_AXILITE_FREQ
  • 50
  • 100
  • 150
  • 200
 100
TX PLL Type
  • CPLL
  • QPLL(GTXE2)
  • QPLL01(GTHE3/4)
  • LCPLL (GTYE5)
  • RPLL (GTYE5)
 C_EXDES_TX_PLL_SELECTION
  • 0
  • 3
  • 6
  • 7
  • 8

0 (GTXE2)

6 (GTHE3/4)

7 (GTYE5)
RX PLL Type
  • CPLL
  • QPLL(GTXE2L)
  • QPLL01(GTHE3/4)
  • LCPLL (GTYE5)
  • RPLL (GTYE5)
 C_EXDES_RX_PLL_SELECTION
  • 0
  • 3
  • 6
  • 7
  • 8

3 (GTXE2)

0 (GTHE3/4)

8 (GTYE5)
Include NIDRU
  • Exclude (Untick)
  • Include (Tick)
 C_EXDES_NIDRU
  • false
  • true
 true
  1. Versal ACAPs support only 100 MHz.