Running the Reference Design (A9 on Zynq) - 3.1 English

HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

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3.1 English
  1. Launch the Xilinx System Debugger by selecting Start > All Programs > Xilinx Design Tools > Vivado 2020.2 > Vivado 2020.2 Tcl Shell.
  2. In the Xilinx command shell window, change to the Example Design Project directory.
    Vivado% cd ./<IP instance name>_ex
  3. Invoke Xilinx System Debugger (xsdb).
    Vivado% xsdb
  4. Establish connections to debug targets.
    xsdb% connect
  5. List all available JTAG targets.
    xsdb% targets
      1 APU
      2* ARM Cortex-A9 MPCore #0 (Suspended)
      3 ARM Cortex-A9 MPCore #1 (Suspended)
      4 xc7z045
  6. Download the bitstream to the FPGA.
    xsdb% source <Vitis Install folder>/scripts/vitis/util/zynqutils.tcl
    xsdb% targets -set 1 (APU)
    xsdb% rst -system
    xsdb% after 3000
    xsdb% target -set 4 (xc7z045)
    xsdb% fpga -file ./<IP instance name>_ex.runs/impl_1/exdes_wrapper.bit
  7. Set the target processor.
    xsdb% targets -set 1 (APU)
    xsdb% loadhw ./<vitis_workspace>/<platform_name>/hw/exdes_wrapper.xsa
    xsdb% targets -set 1 (APU)
    xsdb% ps7_init
    xsdb% ps7_post_config
    xsdb% targets -set 2 (ARM Cortex-A9 MPCore #0)
  8. Download the software .elf to the FPGA.
    xsdb% dow ./<vitis_workspace>/<application_name>_1/Debug/<application_name>_1.elf
  9. Run the software.
    xsdb% con
  10. Exit the XSDB command prompt.
    xsdb% exit
    Important: When using the TB-FMCH-HDMI4K example design with the KCU105 board, you must set the FMC VADJ_1V8 Power Rail before programing the FPGA with the bitstream generated in the Example Design flow. The following topic shows how to set the VADJ power rail when using the KCU105 board. For more details about the KCU105 board, see the KCU105 Board User Guide (UG917).