Running the Reference Design (A72 on Versal) - 3.1 English

HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

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3.1 English
  1. Launch the Xilinx System Debugger by selecting Start > All Programs > Xilinx Design Tools > Vivado 2020.2 > Vivado 2020.2 Tcl Shell.
  2. In the Xilinx command shell window, change to the Example Design Project directory.
    vivado% cd ./<IP instance name>_ex
  3. Invoke Xilinx System Debugger (xsdb).
    Vivado% xsdb
  4. Establish connections to debug targets.
    xsdb% connect
  5. List all available JTAG targets.
    xsdb% targets
    1 Versal vjtag40
        2 RPU (PS POR is active)
            3 Cortex-R5 #0 (PS POR is active)
            4 Cortex-R5 #1 (PS POR is active)
        5 APU (FPD domain isolation)
           6 Cortex-A72 #0 (FPD domain isolation)
           7 Cortex-A72 #1 (FPD domain isolation)
        8 PPU
           9 MicroBlaze PPU (Sleeping after reset)
        10 PSM
        11 PMC
        12 PL
  6. Download the bitstream to the FPGA.
    xsdb% device program ./<IP instance name>_ex.runs/impl_1/exdes_wrapper.pdi
    xsdb% after 1000
  7. Set the target processor.
    xsdb% targets -set -filter {name =~ "Cortex-A72 #0"}
    xsdb% rst -proc
    xsdb% after 1000
  8. Download the software .elf to the FPGA.
    xsdb% dow ./<vitis_workspace>/<application_name>_1/Debug/<application_name>_1.elf
  9. Run the software.
    xsdb% con
  10. Exit the XSDB command prompt.
    xsdb% exit