AXI4-Stream Video Interface - 3.1 English

HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

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3.1 English

The following table shows the signals for AXI4-Stream video output interface. This interface is an AXI4-Stream master interface and runs at the s_axis_video_aclk clock rate. The data width is user-configurable in the Vivado IDE by setting Max Bits Per Component (BPC) and Number of Pixels Per Clock on Video Interface (PPC).

Table 1. AXI4-Stream Video Interface
Name I/O Width Description
s_axis_video_aclk I 1 AXI4-Stream clock
s_axis_video_aresetn I 1 Reset (Active-Low)
VIDEO_OUT_tdata O (int((3*BPC*PPC+7)/8))*8 Data
VIDEO_OUT_tlast O 1 End of line
VIDEO_OUT_tready I 1 Ready
VIDEO_OUT_tuser O 1 Start of frame
VIDEO_OUT_tvalid O 1 Valid
  1. The Video Data width for AXI4-Stream interface is byte aligned. For example, for 10 bpc, 2 ppc, the data width is 64 bits.