Clocks and Resets - 3.1 English

HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

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3.1 English

The following table provides an overview of the clocks and resets. See Clocking and Resets for more information.

Table 1. Clocks and Resets
Name I/O Width Description
s_axi_cpu_aclk I 1 AXI4-Lite CPU control interface clock.
s_axi_cpu_aresetn I 1 Reset, associated with s_axi_cpu_aclk (active-Low). The s_axi_cpu_aresetn signal resets the entire subsystem including the data path and AXI4-Lite registers.
s_axis_video_aclk I 1 AXI4-Stream video output clock.
s_axis_video_aresetn I 1 Reset, associated with s_axis_video_aclk (active-Low). Resets the AXI4-Stream data path for the video output.
s_axis_audio_aclk I 1 AXI4-Stream Audio output clock. (The audio streaming clock must be greater than or equal to 128 times the audio sample frequency)
s_axis_audio_aresetn I 1 Reset, associated with s_axis_audio_aclk (active-Low). Resets the AXI4-Stream data path for the audio output.
link_clk I 1 HDMI Link data output clock. This connects to the Video PHY Controller /HDMI GT Subsystem link clock output.
video_clk I 1 Clock for the native video interface.
  1. The reset should be asserted until the associated clock becomes stable.