Compliance - 3.1 English

HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

Document ID
Release Date
3.1 English

HDCP compliance has been performed with the following DCP certified test equipment:

  • SimplayLabs SL8800
    • HDCP 1.4: 1A, 1B, 2C
    • HDCP 2.3: 1A, 1B, 2C
  • Quantum Data QD980
    • HDCP 2.2: 1A, 1B, 2C

PCB Recommendation

TMDS DATA PCB trace rules necessary to meet HDMI compliance requirements for the TMDS181 and SN68DP159 (only when TX is used) device are as follows:

Inter-pair skew for DATA[0:2] lanes must be:

  • Max 10 ps inter-pair skew FPGA->retimer.
  • Max 10 ps inter-pair skew retimer->connector.

Intra-pair skew for DATA[0:2] lanes must be:

  • Max 1 ps intra-pair skew FPGA->retimer.
  • Max 1 ps intra-pair skew retimer->connector.
  • Target impedance to be 100Ω ±7% (Max ±10%).
    • A single excursion is permitted out to a max/min of 100Ω ±25% and of a duration less than 250 ps.

For HDMI subsystems in high density designs the default PCB recommendations for the decoupling capacitors might not be sufficient. This is especially true for pipelines that are run on the same clock. Make sure to validate your design requirements prior to creating a PCB. For more information see the UltraScale Architecture PCB Design User Guide (UG583) for your architecture.