Running the Reference Design (A53 on Zynq UltraScale+ Devices) - 3.1 English

HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

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3.1 English
  1. Launch the Xilinx System Debugger by selecting Start > All Programs > Xilinx Design Tools > Vivado 2020.2 > Vivado 2020.2 Tcl Shell.
  2. In the Xilinx command shell window, change to the Example Design Project directory:
    Vivado% cd ./<IP instance name>_ex
  3. Invoke Xilinx System Debugger (xsdb).
    Vivado% xsdb
  4. Establish connections to debug targets.
    xsdb% connect
  5. List all available JTAG targets.
    xsdb% targets
      1 PS TAP
      2 PMU
      3 PL
      4 PSU
      5 RPU (Reset)
      6 Cortex-R5 #0 (RPU Reset)
      7 Cortex-R5 #1 (RPU Reset)
      8 APU
      9* Cortex-A53 #0 (Running)
      10 Cortex-A53 #1 (Power On Reset)
      11 Cortex-A53 #2 (Power On Reset)
      12 Cortex-A53 #3 (Power On Reset) 
    Note: The target number for PSU, PL, APU and Cortex™-A53 might be different. Run the targets and ensure they are using the correct target number.
  6. Download the bitstream to the FPGA .
    xsdb% target -set 3 (PL)
    xsdb% fpga -file ./<IP instance name>_ex.runs/impl_1/exdes_wrapper.bit
    xsdd% after 2000
  7. Set the target processor.
    xsdb% target -set 9 (Cortex-A53 #0)
    xsdb% rst -processor
    xsdb% dow ./<vitis_workspace>/<platform_name>/export/<platform_name>/sw/<platform_name>/boot/fsbl.elf
    xsdb% after 1000
    xsdb% con
    xsdb% after 1000
    xsdb% stop
    xsdb% after 1000
    Note: The target number for PSU, PL, and APU running Cortex-A53 might be different, to ensure that the associated target numbers are correct, re-run step 5: List all available JTAG targets.
  8. Download the software .elf to the FPGA .
    xsdb% dow ./<vitis_workspace>/<application_name>_1/Debug/<application_name>_1.elf
  9. Run the software.
    xsdb% con
  10. Exit the XSDB command prompt.
    xsdb% exit