| Subsystem Facts Table | |
|---|---|
| Subsystem Specifics | |
| Supported Device Family 1 |
UltraScale+™ ™ Families (GTHE4, GTYE4) UltraScale™ ™ Architecture (GTHE3) Zynq-7000 SoC 7 series (GTXE2) 2 Artix®-7 (GTPE2) 2 Versal™ ACAPs (GTYE5) |
| Supported User Interfaces | AXI4-Lite, AXI4-Stream |
| Resources | |
| Provided with Subsystem | |
| Design Files | RTL |
| Example Design | Vivado® IP integrator and associated software application example |
| Test Bench | Not Provided |
| Constraints File | XDC |
| Simulation Model | Not Provided |
| Supported S/W Driver 3 | Standalone, Linux |
| Tested Design Flows 4 | |
| Design Entry | Vivado® Design Suite |
| Simulation | Not Provided |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54546 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Xilinx Support web page | |
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