Status and Control Data Channel (SCDC) - 3.1 English

HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

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3.1 English

The subsystem supports the following two bits in the SCDC register address offset 0x20 for TMDS configurations (Table 10-19 of the HDMI 2.0 specification).

  • Bit 1: TMDS_Bit_Clock_Ratio
  • Bit 0: Scrambling_Enable

Two APIs are available in the driver to use this feature.

  • XV_HdmiRx_DdcScdcEnable is used to enable the SCDC register
  • XV_HdmiRx_DdcScdcClear is used to clear the SCDC register